The present invention relates to the field of semiconductor technology. Some embodiments of the invention are directed to device structures and manufacturing methods for making metal gate stacks for CMOS devices.
As critical dimensions shrink in metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), short channel effect (SCE) has become a critical issue. FinFET (Fin Field Effect Transistor) has a good gate control capability to effectively suppress the short channel effect. Furthermore, the FinFET device can reduce random dopant fluctuation (RDF) and improve the stability of the device. Therefore, the design of a small-sized semiconductor element often employs a FinFET device.
The gate work function plays an important role in the threshold voltage of FinFET devices. In the 14 nm HKMG (high-k+metal gate) FinFET device of the process, a low temperature process (for example, 100° C.) is often used to deposit an N-type work function metal layer. However, at low temperature, byproducts generated during deposition of the N-type work function metal layer are difficult to remove, and would impact a high-K dielectric layer, thereby affecting the device performance. Thus, high-temperature processes (for example 400° C.) have been proposed for the deposition of an N-type work function metal layer. However, the inventor discovered that, in conventional devices, the work function of an N-type work function metal layer tends to be too high, leading to the threshold voltage NMOS device being abnormally high.